Semiconductor devices, such as power MOS (metal oxide semiconductor) devices used as electric switches for high frequency PWM (pulse width modulation) applications such as voltage regulators and/or as load switches in power applications typically include a semiconductor die, with thousands of elemental transistors formed therein, and a package for housing and protecting the die and for providing connections to terminals formed on the die. In many applications, it is highly desirable to keep the footprint of the packaged device as small as possible, such as in mobile and other small electronic applications. For a typical packaged power MOS device, the ratio of the die size to the overall package size is typically about 25-50%, meaning that with some packages, the packaged product has a footprint that is about 4 times larger than the packaged die.
In addition to the increased size of the finished product attributable to the packaging, packaging also adds parasitic inductances, capacitances and resistances that can adversely affect device performance, such as the on-resistance (Rds,on) of the device. Packaging also adds an additional thermal barrier between the die and its environment, which affects heat dissipation.
Given the problems associated with packaging semiconductor devices, there is a desire for so-called chip-scale devices. These devices have no packaging formed around the die, although passivation layer(s) may be utilized. Rather, metallization layers are formed directly on the die and solder bumps are coupled to the metallization layers, such as through connection pads. These solder bumps are formed on only one side of the finished device for coupling to, for example, printed circuit boards.
Power MOS devices have not been considered good candidates for the chip-scale approach, as power MOS devices typically utilize vertical current flow, which dictates that connections are made to both sides of the semiconductor die. Notwithstanding the foregoing, at least one chip-scale power MOSFET (MOS field effect transistor) has been proposed in U.S. Published Patent Application No. 2005/0017299A1 to Shen, the entirety of which is hereby incorporated by reference herein. Shen proposes a power MOS device with purely lateral current flow, so that all connection terminals can be formed on the top side of the die. In so doing, Shen employs a complex multilevel bus structure for collecting and distributing the device current. The design necessarily employs a very dense bus structure, i.e., it requires a high number of bus stripes, so bus stripes are made very narrow and thin, providing a consequent resistive voltage drop. This voltage drop, in turn, leads to the de-biasing effect where gate-source driving potential is weakened locally at some transistor cells. Still further, the purely lateral current flow device structure affords equal silicon area to both the source and drain of each transistor formed in the die, which is very area consumptive.
Therefore, there remains a need for an improved chip-scale (or near chip-scale) semiconductor device, and particularly an improved chip-scale (or near chip-scale) power MOS device.